1. Field of the Invention
The present invention relates to power FET devices including LDMOS FET devices. More specifically, the present invention relates to compensating for AM/PM non-linearities in such devices.
2. Background
FIG. 1A is an overall plan view of an exemplary geometry for a conventional high power laterally diffused metal oxide semiconductor (LDMOS) field effect transistor (FET) device. The illustrated device includes three active chips 110. Each active chip 110 contains a plurality of gate-drain pairs including gate-drain pairs 151, 152, 153. Reference numbers for the remaining GDPs in the active chips 110 have been omitted for clarity. FIG. 1B is a magnified cross section of an LDMOS FET. Each of the gate-drain pairs (GDPs) includes a gate 195 (indicated by a suffix G in FIG. 1A) and a drain 196 (indicated by a suffix D in FIG. 1A). The gate and drain regions are indicated by the suffixes xe2x80x9cGxe2x80x9d and xe2x80x9cDxe2x80x9d in FIG. 1A.
LDMOS devices incorporate a deep p+ region 190 or xe2x80x9cp+ sinkerxe2x80x9d that connects through to a bulk p+ region 191 on the bottom of the die. The source terminal (not shown) is electrically connected to this bulk p+ region 191 of the active chip 110. Returning now to FIG. 1A, the gate terminal (not shown) of the device is connected to a gate bond pad 120 in any conventional manner (using, e.g., a gold wire). A conductor 121 provides an electrically conductive path between the gate bond pad 120 and each of the gate regions 151G, 152G, 153G in the GDPs 151, 152, 153. Similarly, the drain terminal (not shown) of the device is connected to a drain bond pad 130 in any conventional manner, and a conductor 131 provides an electrically conductive path between the drain bond pad 130 and each of the drain regions 151D, 152D, 153D in the GDPs 151, 152, 153.
The GDPs are arranged in a linear array, and resemble a stack of fingers. Because the gate bond pad 120 is connected to the gate portion of each GDP 151-153, and the drain bond pad 130 is connected to the drain portion of each GDP, the GDPs (taken together with the source) act like a plurality of transistors connected in parallel. In conventional LDMOS devices, the doping levels are uniform for all of the fingers, and the contribution from each of these parallel-connected transistors to the output signal is substantially the same.
FIG. 2 shows how the output power varies with respect to the input power in an example of an LDMOS device. Initially, in region 201, the relationship between the input power and the output power is highly linear. But as the power increases, two compression effects occur. First, an amplitude compression effect occurs because at some point the FET will leave the linear region 201 and enter the saturation region 202, where the increase in output power does not keep up with increases in input power. It should be appreciated that the reference to xe2x80x9csaturationxe2x80x9d is with respect to xe2x80x9csaturationxe2x80x9d of the RF signal, and is not referring to the saturation region of the transistor where the current becomes constant (independent of drain voltage) for a certain gate voltage.
Second, in the saturation region 202, the electrons traveling through the device tend to slow down. As a result, it takes longer for a large amplitude input signal to propagate through the device and arrive at the output than it does for small and medium amplitude input signals. This increase in travel time appears as a phase shift at the output. This effect is known as AM/PM distortion (amplitude modulation to phase modulation distortion) because large amplitude signals are distorted by a phase shift that is not experienced by small and medium amplitude signals.
Operating LDMOS devices in class AB mode provides high linearity and high efficiency. In general, decreasing the output power in a class AB circuit results in improved linearity.
Thus, there is a need for reducing or eliminating the phase shift experienced by large amplitude input signals during saturation.
The present invention relates to compensating for phase shifts caused by speed variations between different signals that travel through a semiconductor device.
One aspect of the present invention relates to a field effect transistor that includes a plurality of gate regions and a corresponding plurality of drain regions configured to form a plurality of gate-drain pairs. This plurality of gate-drain pairs includes (a) a first set of gate-drain pairs with relatively high threshold turn-on voltages, and (b) a second set of gate-drain pairs with threshold turn-on voltages that are lower than the threshold turn-on voltages of the first set. The field effect transistor also includes a gate bond pad and an electrical connection between the gate bond pad and the plurality of gate regions. This electrical connection is configured so that a path length between the gate bond pad and gate regions in the first set is shorter than a path length between the gate bond pad and gate regions in the second set. The field effect transistor also includes a drain bond pad and an electrical connection between the drain bond pad and the plurality of drain regions. This electrical connection is configured so that a path length between the drain bond pad and drain regions in the first set is shorter than a path length between the drain bond pad and drain regions in the second set. The field effect transistor also includes a source operatively associated with the plurality of gate-drain pairs.
Another aspect of the present invention relates to a field effect transistor that includes a plurality of gate regions and a corresponding plurality of drain regions configured to form a plurality of gate-drain pairs. These gate-drain pairs are arranged in a linear array. The plurality of gate-drain pairs includes (a) a first set of gate-drain pairs with relatively high threshold turn-on voltages located near a reference point on the linear array, and (b) a second set of gate-drain pairs with threshold turn-on voltages that are lower than the threshold turn-on voltages of the first set located away from the reference point. The field effect transistor also includes a gate bond pad located near the reference point, and an electrical connection between the gate bond pad and the plurality of gate regions that is configured so that a path length between the gate bond pad and gate regions in the first set is shorter than a path length between the gate bond pad and gate regions in the second set. The field effect transistor also includes a drain bond pad located near the reference point, and an electrical connection between the drain bond pad and the plurality of drain regions that is configured so that a path length between the drain bond pad and drain regions in the first set is shorter than a path length between the drain bond pad and drain regions in the second set. The field effect transistor also includes a source operatively associated with the plurality of gate-drain pairs.
Another aspect of the present invention relates to a semiconductor device that includes a first terminal and a second terminal, and first and second signal paths between the first terminal and the second terminal. The first signal path has a first length, and the second signal path has a second length that is longer than the first length. Doping variations between the first signal path and the second signal path cause slower-moving carriers to travel through the first path and faster-moving carriers to travel through the second path.